A clean-slate, open ISA for balanced ternary computing. 27-trit words. 27 registers. Fixed-length instructions. 5 configurable ternary logics via LMODE.
↑ ADD r3, r1, r2 — 27-trit instruction (LST-first, t[0] left)
Five formats share the same 27-trit fixed-length word. The opcode sits at t[0]–t[3] (LST) — the decoder starts working before the full word has arrived.
Format B encodes three outcomes in one instruction — P falls through, Z and N each carry an independent PC-relative offset. Zero wasted trits.
The LMODE CSR and STATUS.lx trit select the truth tables
for all logic instructions (TAND, TOR, TNOT, TIMPL) at runtime.
All five IMPL tables are distinct. Same code, different epistemology,
one register write.
CONS, ACONS, and TCMP are LMODE-insensitive — they are ternary-native comparison primitives that form a complete trit-comparison toolkit.
v0.8 adds a dedicated 27-register vector bank (v0..v26) with a
trit-parallel datapath: each lane is a single trit, 27 lanes per word.
Eight new opcodes (+15..+22) amortise fetch/decode over 27 simultaneous
trit operations and expose ternary-native primitives that have no clean
binary equivalent.
The format set is unchanged — vector opcodes reinterpret the existing R-format register fields as v-reg indices. Two opcodes (+23, +24) are reserved for v0.9 (fused multiply-accumulate, gather/scatter). v0.8 is purely additive: existing v0.7 binaries run unmodified.
Ternary ML at 1.58-bit (BitNet-style weights ∈ {−1, 0, +1}) maps directly onto the lane width — one v-reg holds 27 weights, one VMUL + VRED computes a dot product without packing.
Setnex is not the only balanced ternary project. A small but active community has been building ternary hardware, simulators, and documentation — some for decades. Setnex positions itself among them as an open, logic-configurable ISA, distinct in its goals but indebted to prior art.
The 5500FP is the closest living cousin of Setnex: another balanced ternary RISC ISA with real hardware behind it. The two projects answer different questions, and their differences are worth making explicit.
In short: the 5500FP is a ternary processor of the engineering tradition — rich instruction set, mature tooling, atomics, and real silicon through FPGA. Setnex is a ternary ISA of the logical tradition — minimal core, configurable multi-valued logics, ternary-native control flow, and an open specification. They are complementary, not competing: if you want to run ternary code on real hardware today, look at the 5500FP. If you want to experiment with the epistemology of three-valued reasoning, Setnex is built for that.
setnex-asm / setnex-run, 100% coverage. Tracks v0.7; vector extension (v0.8) not yet implemented.